Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is used as one of the basic building blocks of most modern electronic circuits. Thus, such circuits realize improved performance and lower costs as the performance of the MOS transistor is increased and as the manufacturing costs are reduced.
A typical MOS semiconductor device generally includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by heavily doping the regions with a dopant material of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
A channel region is formed in the semiconductor substrate beneath the gate electrode and between the source and drain regions. The channel is typically lightly doped with a dopant material having a conductivity type opposite to that of the source and drain regions. The gate electrode is generally separated from the substrate by an insulating layer, typically an oxide layer such as SiO.sub.2. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, drain or channel regions. In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to controls the current flow through the channel region. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
MOS devices typically fall in one of two groups depending the type of dopant materials used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
Historically, only one type of device would be fabricated on a single wafer (i.e., only a single technology such as NMOS or PMOS would be used). As larger numbers of devices were formed on a wafer, increases in power density and dissipation inhibited the ability to use only a single technology. In response, complementary MOS (CMOS) technology was developed using both PMOS and NMOS transistors fabricated in a single substrate. While use of CMOS technology solves a number of problems, the technology is significantly more complex with respect to device physics. Moreover, since different types of dopant materials are being used, the complexity and cost of the fabrication process are both increased. For example, different masking and implantation steps are typically required to form doped regions for each type of dopant material in the substrate.
A number of different techniques and fabrication processes may be used to form CMOS devices. With reference to FIGS 1A-1E, one typical CMOS fabrication process will be described. The process depicted is used to form semiconductor structures having lightly doped drain (LDD) regions within the source and drain structures. As is well known, LDD structures are used in the formation of semiconductor devices having short channels in order to overcome problems associated therewith.
As depicted in FIG. 1A, a substrate 101 is divided into two device regions 101A and 101B. The two device regions 101A and 101B are of different conductivity types (n-channel and p-channel, respectively, in the illustrated embodiment) and are used to form the CMOS structures thereon. Different techniques may be used to form the two device regions 101A and 101B. The regions may be formed using an n-well in a p-type substrate, a p-well in an n-type substrate, twin wells in either an n- or p-type of substrate, etc. On the surface of the substrate 101, a field oxide, such as SiO.sub.2, is generally provided to isolate the surface of the two device regions 101A and 101B. One or more gate electrodes 103 are formed on each of the device regions 101A and 101B. In the illustrated example, one gate electrode 103A is formed on the device region 101A and one gate electrode 103B is formed on the device region 101B.
An LDD region in the n-channel device region is first formed by masking the p-channel device region 101B with a mask layer 105 and implanting a relatively low dose of an n-type dopant material 107 into the exposed areas to form lightly doped (i.e., LDD) n-type regions 109 as illustrated in FIG. 1A. A second mask 111 is formed over the n-channel device region 101A and a p-type dopant material 113 is implanted into the p-channel device region 101B to form lightly doped (i.e., LDD) p-type regions 115 in the substrate adjacent the gate electrode 103B.
Following the LDD implants, a spacer layer is formed and etched to form spacers 117 on sidewalls of the gate electrodes 103A and 103B. The p-channel device region 101B is again masked with a mask layer 119 and a heavy dose of an n-type dopant material 121 is implanted into the substrate aligned with the spacers 117A to form heavily doped n-type regions 118A, as illustrated in FIG. 1C. In this manner, LDD structures 123A are formed in the substrate as illustrated in FIG. 1C.
In a manner similar to the n-channel region, the p-channel device region 101B is then exposed while masking the n-channel device region 101A with a mask layer 125. A high dose of a p-type dopant material 118 is implanted into the substrate using spacers 117B for alignment to form heavily doped p-type regions 118B. In this manner, LDD structures 127B are also formed in the p-channel device region 101B.
Following formation of the LDD structures, the mask 125 is typically removed and further processing such as silicidation and interconnect formation is performed. The resulting structure is depicted in FIG. 1E. A more detailed description of the elements and fabrication of LDD source/drain regions may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 354-363.
As noted above, the use of different types of dopant materials significantly increases the complexity of CMOS technology. For example, p-type dopant materials, such as boron, typically diffuse more rapidly in silicon than n-type dopant materials, such as arsenic. This places constraints on the heat treatment of the device and reduces the ability to control the profiles of source/drain regions.
The formation of LDD regions in CMOS devices further increases the complexity of fabricating CMOS devices. For example, the heavily doped n-type and p-type regions 118A and 118B must have adequate conductivity for device performance and sufficient depth to allow the formation of a silicide layer. Using the above conventional techniques to provide adequate conductivity and depth can cause excessive lateral diffusion of the heavily-doped n-type and p-type regions. This excessive lateral diffusion can in some instances overlap the lightly-doped n-type and p-type regions 109 and 115 and reduce the effective channel length.